The invention relates generally to memory arrays, and more particularly to a memory array having one or more bit, i.e., digit, lines buried in the isolation regions such as silicon-trench-isolation (STI) regions.
To accommodate continuing consumer demand for integrated circuits that perform the same or additional functions and yet have a reduced size as compared with available circuits, circuit designers continually search for ways to reduce the size of the memory arrays within these circuits without sacrificing array performance. For example, one known technique for reducing the layout area of a Dynamic Random Access Memory (DRAM) array is to stack storage capacitors above memory cells. Typically, the memory cells are formed in adjacent pairs, where each pair shares a common source/drain region that is connected to a respective digit line. Because the digit lines are disposed above the stack capacitors, and thus above the common source/drain regions, conductive vias are needed to connect the digit lines to the respective common source/drain regions. Therefore, these vias must extend through or adjacent to the plates of the stacked storage capacitors.
A problem with such a stacked-capacitor memory array is that the area of each memory cell, and thus the area of the memory array itself, often cannot be reduced without reducing the capacitances of the stacked capacitors beyond acceptable limits. Because capacitance is proportional to the overlap area of the capacitor plates, the plates of the stacked capacitors must have an overlap area that is large enough to give these capacitors the desired storage capabilities. But the vias that connect the common source/drain regions to the digit lines also have minimum dimensions that are proportional to the minimum feature size of the utilized semiconductor process. Therefore, because a via extends through a hole in a respective pair of stacked-capacitor plates, the minimum total area of a plate is the sum of the minimum required overlap area and the minimum required cross-section area of the intersecting via.
To solve this problem, the article xe2x80x9cBuried Bit-Line Cell for 64 MB DRAMS,xe2x80x9d proposes burying the bit-lines in the substrate. But, because these bit-lines are formed after the field oxide regions and because the contacts between the bit-lines and the respective memory cells are also buried in the substrate, the resulting reduction in memory-cell area falls short of the maximum obtainable reduction for a given minimum feature size.
Another problem is that, even if it were possible to reduce the area of such a memory array by the maximum obtainable reduction, it would be difficult, if not impossible, to implement a folded-digit-line architecture in such a reduced-area array. In such an architecture, there are typically four word lines that extend over a memory cell pair, as compared with two word lines in a shared-digit-line architecture. Like the vias, the word lines have minimum dimensions that are dictated by the minimum feature size. Therefore, if the area of a memory cell is reduced too much, adjacent word lines may become short-circuited to each other, thus rendering the memory array defective.
In accordance with one aspect of the invention, a memory array includes a semiconductor substrate, an isolation trench located in the substrate, and a conductor that is located in the trench. The array also includes a memory cell that is coupled to the conductor in the trench. In another embodiment of the invention, the conductor is a digit line that is coupled to a source/drain region of the memory cell.
Thus, where the conductor in the isolation trench is a digit line, no digit-line vias are required. The freed-up space can be used to increase the size, and thus the capacitances, of the stacked capacitors. Or, it can be used to reduce the size of the memory cells without reducing these capacitances.